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<a href="#" id="menu-submit"><span></span>Menu</a></div></div></div></div></div></div></div></header><main id="main" role="main"><div class="section-wrapper cf"><div class="section-wrapper-content cf"><section class="section default-01 design-01 wsection-white"><div class="section-bg"><div class="section-bg-layer"></div><div class="section-bg-layer section-bg-overlay"></div></div><div class="section-inner"><div class="content cf wnd-no-cols"><div><div class="text cf design-01"><div class="container"><div class="vc_row vc_row-fluid boxed"><div class="wpb_column vc_column_container vc_col-sm-12"><div class="vc_column-inner "><div class="wpb_wrapper"><div class="wpb_text_column wpb_content_element " ><div class="wpb_wrapper"><h1 style="text-align: center;"><span style="font-weight: 400; color: #ff0000;">RISC-V</span></h1><h3 style="text-align: left;"><span style="font-weight: 400; color: #000000;">What is RISC-V ?</span></h3><p><span style="font-weight: 400;"><a href="https://www.ssla.co.uk">RISC-V</a> is an open source instruction set architecture. Based on reduced instruction set computers. Which means RISC-V provides CPU architecture which is free to use and the CPU vendor does not need to provide a license fee in order to use this architecture. The need for open source hardware architecture arises years after using few of the available architectures. There are many advantages of <a href="https://www.ssla.co.uk/buy/">open source hardware</a> architecture, a few of them are mentioned below.</span></p><ul><li style="font-weight: 400;"><span style="font-weight: 400;">No licensing fee for the architecture.</span></li><li style="font-weight: 400;"><span style="font-weight: 400;">Easy customisation of the architecture based on the clients requirements.</span></li><li style="font-weight: 400;"><span style="font-weight: 400;">Can update the architecture with changing technology.</span></li><li style="font-weight: 400;"><span style="font-weight: 400;">Saves time.</span></li><li style="font-weight: 400;"><span style="font-weight: 400;">Provide enhancement to existing architectures.</span></li></ul><p><span style="font-weight: 400;"><a href="https://en.wikipedia.org/wiki/Reduced_instruction_set_computer">RISC</a> started in 1980 to reduce the number of instructions needed in a CPU. As we know the chipset market is increasing year on year with roughly 7 billion chipsets used worldwide as of 2020 in many devices like mobile phones, cameras, smart meters, sensors, drones, wifi, laptops, cloud servers the list goes on and on. And the number of devices used is expected to grow 3-4 times more in the next 5 – 10 years. Hence with growing demand for more and more technology and innovation. A push for open source hardware architecture is increasing.</span></p><p><span style="font-weight: 400;">An Instruction is usually an assembly language code that tells the CPU what to do since each CPU has a bunch of register and memory locations architecture vendor provides instructions to control the CPU. For example </span><span style="font-weight: 400;">move a to b </span><span style="font-weight: 400;">This is a simple instruction which tells the CPU to move the contents of register a to b. So there are 1000’s of instructions that are made available by the vendor who designs the architecture. Now a good CPU architecture will provide almost 99% perfect architecture and assembly instructions to operate the CPU. But even then due to the changing technology, innovations and use cases in the real work. The architecture vendor cannot guarantee a 100% instructions set that works perfectly. Due to limited reasons. Let’s take a look at one of the x86 assembly programs. </span></p><p><span style="font-weight: 400;">————————————————-</span></p><p><span style="font-weight: 400;"> global _start</span></p><p><span style="font-weight: 400;"> section .text</span></p><p><span style="font-weight: 400;">_start: mov ax, 1 ; system call for write function</span></p><p><span style="font-weight: 400;"> mov di, 1 ; file handle 1 is stdout for display</span></p><p><span style="font-weight: 400;"> mov si, message ; address of string to output to move</span></p><p><span style="font-weight: 400;"> mov dx, 13 ; number of bytes to move</span></p><p><span style="font-weight: 400;"> syscall ; invoke system to do the write operation</span></p><p><span style="font-weight: 400;"> mov ax, 60 ; system call for exit here</span></p><p><span style="font-weight: 400;"> xor di, di ; exit from code 0</span></p><p><span style="font-weight: 400;"> syscall ; invoke OS system to exit</span></p><p><span style="font-weight: 400;"> section .data</span></p><p><span style="font-weight: 400;">message: db “Hello to the World”, 15 ; Add the newline at the end</span></p><p><span style="font-weight: 400;">————————————————-</span></p><p><span style="font-weight: 400;">The above program contains as you can see instructions and these instructions will be converted into binary format logic 0 or 1 before they can run on the CPU. But in the modern world we do not see these instruction sets. Today the world uses high level languages like C, C++, Java, .net python and so on. With an increasing number of applications developers just learn one of the high level languages to develop their applications. And do not worry about the underlying architecture or instruction set.</span></p><p><span style="font-weight: 400;">In reality these high level languages are compiled and converted into machine level language called the assembly language by the compilers developed by the architecture vendors. Hence there is a slight gap between high level developers and the architecture vendors. In order to fill this gap RISC-V made the architecture open source hardware architecture. So that developers from any level high level and low level can work closely to understand the behaviour of the CPU. An example is we have seen many times our phone, laptop freezes or hangs. By closing the gap between engineers and developers RISC-V can achieve high success in the throughput. </span></p><h3 style="text-align: left;"><span style="font-weight: 400; color: #000000;">Why is RISC-V gaining popularity ?</span></h3><p><span style="font-weight: 400;">There are many reasons why it is gaining popularity; a few of them are mentioned below.</span></p><ul><li style="font-weight: 400;"><span style="font-weight: 400;">Open source architecture Since the architecture is open many developers can see how the 1s and 0s are flowing in the CPU. and suggest any improvements or issues that occur during the experimental phase or testing phase. And add new IP as technology, innovation advances over time.</span></li><li style="font-weight: 400;"><span style="font-weight: 400;">Trailer the architecture specific the clients workload with the past architecture it was impossible to tailor the architecture even if there was a need to do so. With open source architecture now they can tailor however they want as per their workload. Which helps semiconductor manufacturers to save time as they need not wait for new innovation or new architecture to be released by the architecture vendors.</span></li><li style="font-weight: 400;"><span style="font-weight: 400;">Mostly 90% of the cloud servers use Intel which means it is more easily hacked by attackers. Intel releases patches to stop these attacks from hackers cause a huge hit in the performance of the servers. But with RISC-V architecture every vendor can have their own version of security embedded in the architecture making it difficult for attackers.</span></li><li style="font-weight: 400;"><span style="font-weight: 400;">Cost of using the architecture is completely free. As we are aware of the growth of technology and innovation, everyone is bound to use a smart device in some way either in a car or in home or in the office or around us. When semiconductor vendors pay for a license of architecture it increases the overall cost of the end device. With open source architecture silicon vendors can provide smart devices necessary in day to day use at a reasonable price.</span></li></ul><h3 style="text-align: left;"><span style="font-weight: 400; color: #000000;">List of RISC-V evaluation boards.</span></h3><p><span style="font-weight: 400;">There are many RISC-V based chipset some of them are SoC some of them are FPGA chipset. Below table specifies some of the RISC-V architecture based CPU chipsets.</span></p><table><tbody><tr><td><b>Name</b></td><td><b>Supplier</b></td><td><b>Links</b></td><td><b>Core</b></td><td><b>ISA</b></td><td><b>OS</b></td><td><b>Devkit</b></td></tr><tr><td><span style="font-weight: 400;">FE310-G000</span></td><td><span style="font-weight: 400;">SiFive</span></td><td><span style="font-weight: 400;">Datasheet</span></td><td><span style="font-weight: 400;">E31</span></td><td><span style="font-weight: 400;">RV32IMAC</span></td><td><span style="font-weight: 400;">RTOS</span></td><td><span style="font-weight: 400;">HiFive1</span></td></tr><tr><td><span style="font-weight: 400;">FE310-G002</span></td><td><span style="font-weight: 400;">SiFive</span></td><td><span style="font-weight: 400;">Product page</span></td><td><span style="font-weight: 400;">E31</span></td><td><span style="font-weight: 400;">RV32IMAC</span></td><td><span style="font-weight: 400;">RTOS</span></td><td><span style="font-weight: 400;">HiFive1 Rev B</span></td></tr><tr><td><span style="font-weight: 400;">Freedom U540</span></td><td><span style="font-weight: 400;">SiFive</span></td><td><span style="font-weight: 400;">Product page</span></td><td><span style="font-weight: 400;">U54 (4 cores), E51 (1 management core)</span></td><td><span style="font-weight: 400;">RV64GC (application cores), RV64IMAC (management core)</span></td><td><span style="font-weight: 400;">Linux</span></td><td><span style="font-weight: 400;">HiFive Unleashed development board</span></td></tr><tr><td><span style="font-weight: 400;">GAP8</span></td><td><span style="font-weight: 400;">GreenWaves Technologies</span></td><td><span style="font-weight: 400;">Product page</span></td><td><span style="font-weight: 400;">PULP / 1 + 8 RI5CY</span></td><td><span style="font-weight: 400;">RV32IMC (+ Priviledged and custom ISA extensions)</span></td><td><span style="font-weight: 400;">RTOS</span></td><td><span style="font-weight: 400;">GAPuino development board</span></td></tr><tr><td><span style="font-weight: 400;">K210</span></td><td><span style="font-weight: 400;">Kendryte</span></td><td><span style="font-weight: 400;">Product page, Datasheet, GitHub</span></td><td><span style="font-weight: 400;">K210</span></td><td><span style="font-weight: 400;">RV64GC</span></td><td><span style="font-weight: 400;">Linux</span></td><td><span style="font-weight: 400;">KD233 development board, Sipeed MAIX/M1 development boards</span></td></tr><tr><td><span style="font-weight: 400;">RV32M1</span></td><td><span style="font-weight: 400;">NXP</span></td><td><span style="font-weight: 400;">Reference Manual and Datasheet</span></td><td><span style="font-weight: 400;">RI5CY + Zero RI5CY + Arm Cortex M4F + Arm Cortex M0+</span></td><td><span style="font-weight: 400;">RV32IMC</span></td><td><span style="font-weight: 400;">RTOS</span></td><td><span style="font-weight: 400;">VEGAboard</span></td></tr><tr><td><span style="font-weight: 400;">RavenRV32</span></td><td><span style="font-weight: 400;">efabless</span></td><td><span style="font-weight: 400;">Datasheet, GitHub</span></td><td><span style="font-weight: 400;">PicoRV32</span></td><td><span style="font-weight: 400;">RV32IMAC</span></td><td><span style="font-weight: 400;">RTOS</span></td><td><span style="font-weight: 400;">RavenRV32 DevKit</span></td></tr><tr><td><span style="font-weight: 400;">PolarFire SoC</span></td><td><span style="font-weight: 400;">Microchip</span></td><td><span style="font-weight: 400;">Product Page, IDE with Renode platform</span></td><td><span style="font-weight: 400;">U54 (4 cores), E51 (management core)</span></td><td><span style="font-weight: 400;">RV64GC(U54), RV64IMAC(E51)</span></td><td><span style="font-weight: 400;">Linux</span></td><td><span style="font-weight: 400;">HiFive Unleashed Expansion Board, PolarFire SoC</span></td></tr><tr><td><span style="font-weight: 400;">GD32VF103</span></td><td><span style="font-weight: 400;">GigaDevice</span></td><td><span style="font-weight: 400;">Product listing,Datasheets</span></td><td><span style="font-weight: 400;">Bumblebee Core</span></td><td><span style="font-weight: 400;">RV32IMAC</span></td><td><span style="font-weight: 400;">RTOS</span></td><td><span style="font-weight: 400;">GD32VF103V-EVAL, Longan Nano etc.</span></td></tr></tbody></table><p>The above table does not specify all the FPGA, VHDL hardware.</p><h3 style="text-align: left;"><span style="font-weight: 400; color: #000000;">RISC-V vs ARM vs x86 Comparison.</span></h3><p>Bellow is the list of comparison between custom ISA, Licensed ISA and Open source ISA.</p><table><tbody><tr><td></td><td><b>Custom ISA</b></td><td><b>Licensed ISA</b></td><td><b>Licensed ISA with </b><b>architecture license</b></td><td><b>Open-Source ISA</b></td></tr><tr><td><b>Design Flexibility</b></td><td><span style="font-weight: 400;">High</span></td><td><span style="font-weight: 400;">Low</span></td><td><span style="font-weight: 400;">Moderate to high</span></td><td><span style="font-weight: 400;">High</span></td></tr><tr><td><b>License Fees</b></td><td><span style="font-weight: 400;">None</span></td><td><span style="font-weight: 400;">$0 to millions</span></td><td><span style="font-weight: 400;">$0 to millions</span></td><td><span style="font-weight: 400;">None</span></td></tr><tr><td><b>Royalty Fees</b></td><td><span style="font-weight: 400;">None</span></td><td><span style="font-weight: 400;">0 to a few %</span></td><td><span style="font-weight: 400;">0 to a few %</span></td><td><span style="font-weight: 400;">0 to a few %</span></td></tr><tr><td><b>Available Software</b></td><td><span style="font-weight: 400;">None to little</span></td><td><span style="font-weight: 400;">Moderate to extensive</span></td><td><span style="font-weight: 400;">Moderate to extensive</span></td><td><span style="font-weight: 400;">Little to moderate</span></td></tr><tr><td><b>Processor Cores</b></td><td><span style="font-weight: 400;">Custom</span></td><td><span style="font-weight: 400;">Standard</span></td><td><span style="font-weight: 400;">Standard to custom</span></td><td><span style="font-weight: 400;">Custom or standard</span></td></tr><tr><td><b>Hardware Engineering Costs</b></td><td><span style="font-weight: 400;">High</span></td><td><span style="font-weight: 400;">Low</span></td><td><span style="font-weight: 400;">Low to moderate</span></td><td><span style="font-weight: 400;">High</span></td></tr><tr><td><b>Software Engineering Costs</b></td><td><span style="font-weight: 400;">High</span></td><td><span style="font-weight: 400;">Low to moderate</span></td><td><span style="font-weight: 400;">Low to moderate</span></td><td><span style="font-weight: 400;">Moderate to high</span></td></tr><tr><td><b>DevelopmentTime</b></td><td><span style="font-weight: 400;">Long</span></td><td><span style="font-weight: 400;">Short</span></td><td><span style="font-weight: 400;">Short to moderate</span></td><td><span style="font-weight: 400;">Long</span></td></tr><tr><td><b>Manufacturability Risk</b></td><td><span style="font-weight: 400;">High</span></td><td><span style="font-weight: 400;">Low</span></td><td><span style="font-weight: 400;">Low to moderate</span></td><td><span style="font-weight: 400;">Moderate to high</span></td></tr><tr><td><b>Time-to-Market</b></td><td><span style="font-weight: 400;">Long</span></td><td><span style="font-weight: 400;">Short</span></td><td><span style="font-weight: 400;">Short to moderate</span></td><td><span style="font-weight: 400;">Moderate to high</span></td></tr></tbody></table></div></div><div class="vc_btn3-container red-button vc_btn3-inline" >
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